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-- Company: 
-- Engineer:
--
-- Create Date:   09:27:15 11/16/2010
-- Design Name:   
-- Module Name:   E:/Dev/VHDL/state_machine/tb_core_left_register_set_cmd_wr.vhd
-- Project Name:  state_machine
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: CORE_LEFT
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
USE work.constants.all;

ENTITY tb_core_left_register_set_mon_len IS
END tb_core_left_register_set_mon_len;
 
ARCHITECTURE behavior OF tb_core_left_register_set_mon_len IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT CORE_LEFT
    PORT(
         clk : IN  std_logic;
         reset : IN  std_logic;
         data_in : IN  std_logic_vector(31 downto 0);
         addr : IN  std_logic_vector(9 downto 0);
         rd_en : IN  std_logic;
         wr_en : IN  std_logic;
         data_out : OUT  std_logic_vector(31 downto 0);
         req_irq : OUT  std_logic;
         shift : OUT  std_logic;
         capture : OUT  std_logic;
         update : OUT  std_logic;
         gwen : OUT  std_logic;
         resetn : OUT  std_logic;
         tdi : OUT  std_logic;
         tdo : IN  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal clk : std_logic := '0';
   signal reset : std_logic := '1';
   signal data_in : std_logic_vector(31 downto 0) := (others => '0');
   signal addr : std_logic_vector(9 downto 0) := (others => '0');
   signal rd_en : std_logic := '0';
   signal wr_en : std_logic := '0';
   signal tdo : std_logic := '0';

 	--Outputs
   signal data_out : std_logic_vector(31 downto 0);
   signal req_irq : std_logic;
   signal shift : std_logic;
   signal capture : std_logic;
   signal update : std_logic;
   signal gwen : std_logic;
   signal resetn : std_logic;
   signal tdi : std_logic;

   -- Clock period definitions
   constant clk_period : time := 1 us;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: CORE_LEFT PORT MAP (
          clk => clk,
          reset => reset,
          data_in => data_in,
          addr => addr,
          rd_en => rd_en,
          wr_en => wr_en,
          data_out => data_out,
          req_irq => req_irq,
          shift => shift,
          capture => capture,
          update => update,
          gwen => gwen,
          resetn => resetn,
          tdi => tdi,
          tdo => tdo
        );

   -- Clock process definitions
   clk_process :process
   begin
		clk <= '0';
		wait for clk_period/2;
		clk <= '1';
		wait for clk_period/2;
   end process;
 	
   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100ms.
      wait for 1 us;
	  reset <= '0';
      wait for clk_period*1;
	  
      -- insert stimulus here 
      data_in <= X"ABCDEF01";
	  addr(IRQ_ADDR) <= '1';
	  wr_en <= '1';
	  wait for clk_period*2;
	  rd_en <= '1';
	  wr_en <= '0';
      wait;
   end process;

END;
